Today, nonvolatile memories including EEPROMs (Electrically Erasable Programmable Read Only Memories) are extensively used for, e.g., portable telephones. An EEPROM usually allows only one bit of information to be written to each storage cell transistor. However, to promote size reduction of the device, there should preferably be implemented the multiple-bit configuration of a cell transistor that allows two or more bits of information to be written to the cell transistor.
FIG. 26 of the drawings is a section showing a prior art cell transistor with a multiple-bit configuration. This multiple-bit configuration is taught in U.S. Pat. No. 6,011,725 specifically.
As shown in FIG. 26, the cell transistor, generally 1, has a so-called MONOS (Metal Oxide Nitride Oxide Semiconductor) structure made up of a control gate (metal) 7, a silicon oxide layer (oxide) 6, a silicon nitride layer (nitride) 5, a silicon oxide layer (oxide) 4, and a p-type silicon substrate (semiconductor) 2.
In the cell transistor 1, n-type source/drain regions 3 and 8 each selectively become a source or a drain at various stages of a write-in or a read-out sequence. Stated another way, it is indefinite which of the source/drain regions 3 and 8 functions as a source region or a drain region. In the following description, one of the source/drain regions 3 and 8 that discharges an electric carrier, which may be electrons in this specific case, and the other region will be referred to as a source and a drain region, respectively.
FIG. 27A demonstrates how data is written to the storage cell transistor 1. As shown, the source region 8 is grounded while suitable positive voltages VD1 and VG1 are applied to the drain region 3 and control gate 7, respectively.
In the above condition, an electric field is established between the source region 8 and the drain region 3 and accelerates electrons, so that hot electrons are generated in the vicinity of the drain region 3. The hot electrons thus generated are injected into the silicon nitride layer 5 over the energy barrier of the silicon oxide layer 4 due to collision thereof against phonons and the positive potential of the control gate electrode 7. Because the silicon nitride layer 5 is not conductive, the hot electrons injected into the silicon nitride layer 5 localize in the vicinity of the drain region 3 (referred to as a right bit 208 hereinafter). This condition is representative of a stored-bit state “(1, 0)”.
FIG. 27B shows a condition wherein the source voltage and drain voltage of FIG. 27A are replaced with each other. As shown, the hot electrons injected into the silicon nitride layer 5 localize in the vicinity of the drain region 8 (referred to as a left bit 206 hereinafter). This sets up a storage state (0 1).
FIGS. 28 A through 28 D show four different logical states available with the cell transistor 1 . In a “(1, 1)” state (see FIG. 28 A), electrons are not stored in either one of the right and left bit positions. In a “(0, 0)” state (see FIG. 28D), electrons are stored in both of the right and left bit positions. In this manner, the cell transistor 1 allows two-bit data to be stored therein. However, this data writing sequence is undesirable because the hot electrons cannot be injected into the silicon nitride layer 5 unless the voltage VG1 applied to the control gate 7 is high.
More specifically, for the injection of hot electrons, it is necessary to tunnel hot electrons from the conduction band of the silicon substrate 2 to the conduction band of the silicon oxide layer 4. An energy difference between the above two conduction bands is about 3.2 eV.
However, the hot electrons lose energy on colliding against phonons present in the silicon substrate 2 and cannot be tunneled between the two conduction bands mentioned above even if a voltage of 3.2 V is applied to the control gate 7. In practice, therefore, the voltage VG1 applied to the control gate 7 must be as high as 12 V to 13 V.
While the above high voltage is expected to be applied to the control gate 7 from a highly voltage-resistant transistor included in a decoder circuit (not shown), such a transistor cannot be miniaturized because miniaturization would cause punch-through to occur between the source and the drain of the transistor. It is therefore impossible with the prior art structure described above to reduce the chip size of the entire EEPROM including the decoder circuit.
On the other hand, to read out the data from the cell transistor 1, the voltages applied to the source region 8 and drain region 3 are replaced with each other to measure a drain current while each drain current measured is compared with a reference current value.
In the state “(0, 0)” (see FIG. 28d),electrons localize at both of the right and left bit positions, so that the potential of the silicon nitride layer 5 is lowest among the four states. Consequently, the threshold voltage of the cell transistor 1 becomes highest and causes substantially no drain current to flow. The value of the drain current remains the same even when the voltages applied to the source/drain regions 3 and 8 are replaced, and is almost zero. As a result, the two drain currents measured both are determined to be smaller than the reference current.
In the state “(1, 1)” (see FIG. 28A), electrons are absent at both of the right and left bit positions, so that the potential of the silicon nitride layer 5 is highest among the four states. Consequently, the threshold voltage of the cell transistor 1 becomes lowest among the four states, causing the greatest drain current to flow. The value of the drain current remains the same even when the voltages applied to the source/drain regions 3 and 8 are replaced, and is greatest among the four states. More specifically, the two drain currents measured both are determined to be greater than the reference current.
On the other hand, in the states “(1, 0)” and “(0, 1)” (see FIGS. 28B and 28C, respectively), electrons localize at only one of the right and left bit positions, making the cell transistor 1 asymmetrical in the right-and-left direction. Therefore, the drain currents measured are different from each other when the voltages applied to the source/drain regions 3 and 8 are replaced. It is therefore possible to distinguish the states “(1, 0)” and “(0, 1)” by determining which of the two drain currents is greater (or smaller) than the reference current.
The data reading sequence described above has a drawback that a current window is smaller when the state “(1, 0)” or the state “(0, 1)” is sensed. The current window refers to a difference between the two drain currents measured by replacing the voltages applied to the source/drain regions 3 and 8 in the event of sensing the states (1, 0) and (0, 1).
The current window definitely opens when electrons distinctly localize at the right (or the left) end of the silicon nitride layer 5, i.e., when the cell transistor 1 is clearly asymmetrical.
Asymmetry, however, does not clearly appear in the cell transistor 1 because electrons are distributed in the silicon nitride layer 5 over some breadth. Particularly, when a gate length L (see FIG. 27A) is reduced for reducing the cell size, it is not clear at which of the right and left bit positions electrons localize, further reducing the asymmetry of the cell transistor 1 and therefore the current window. Such a small current window reduces the margins of the drain and reference currents and thereby aggravates incorrect identification of written data.
Another problem with the conventional transistor 1 is that resistance to inter-band tunneling is low, as will be described hereinafter with reference to FIG. 29. FIG. 29 shows a condition wherein the cell transistor 1 is not selected. As shown, to make the cell transistor 1 unselected, a ground potential lower than the potential assigned to read-out is applied to the control gate 7. On the other hand, the positive potential VD1 is applied to the drain of a cell transistor selected. Because the positive potential VD1 is common to all of the cells in the direction of column of the memory device, it is applied to the drain region 3 of the cell transistor 1 as well.
In the condition shown in FIG. 29, a potential difference ΔV between the silicon nitride layer 5 and the drain region 3 is greater than in the case of read-out because the potential of the control gate 7 is lowered. Particularly, when electrons localize in the silicon nitride layer 5, the potential difference ΔV further increases because the electrons lower the potential of the silicon nitride layer 5. If the potential difference ΔV is great, then a tunnel current flows between the drain region 3 and the silicon nitride layer 5 and causes the silicon oxide layer 4 to deteriorate.
Moreover, a great potential difference ΔV produces a strong electric field at the edge of the drain region 3, so that breakdown is apt to occur at the PN junction of the drain region 3 and silicon substrate 2. The breakdown causes hot holes and electrons to appear in pairs, as shown in an enlarged view in a circle. The hot holes are attracted toward the lower potential side (silicon nitride layer 5 side) and therefore passed through the silicon oxide layer 4, deteriorating the layer 4. The low resistance to inter-band tunneling mentioned earlier refers to the circumstances described above.
The present invention is made to solve the problem described above, and it is an object of the present invention to provide a multiple-bit transistor operable with a lower write voltage and a wider current window than the conventional multiple-bit transistor, a semiconductor memory using the same and capable of deleting a charge stored in a floating gate, and a method of driving a multiple-bit transistor.
An EEPROM or similar nonvolatile memory has still another problem left unsolved, as will be described hereinafter. An EEPROM is extensively used for, e.g., a portable telephone. Generally, what is most important to a memory is a low cost for a single bit and therefore a simple memory cell structure.
On the other hand, a matter of primary concern with a memory of the kind described is increasing writing speed. For example, a system that allows the user of a portable telephone to download pieces of music at a convenience store or similar retail store is attracting attention. In such a case, it is desirable for the user to be able to download music data corresponding to a single CD (Compact Disk) within several seconds.
Reducing a write current is considered to be one of possible implementations for increasing writing speed. More specifically, a decrease in write current allows data to be written to a plurality bits of storage cells in parallel for thereby increasing writing speed.
A technology for reducing a write current is disclosed in, e.g., T. Kobayashi et al. “A Giga-Scale Assist-Gate (AG)-AND-Type Flash Memory Cell with 20-MB/s Programming Throughput for Content-Downloading Applications”, International ELECTRON DEVICES Meeting (IEDM) 2001, Washington, D.C., December 2-5, pp. 0.2.2.1-0.2.2.4. The memory cell taught in this document includes a floating gate positioned above the channel region of a MOS semiconductor and a control gate positioned above the floating gate. Part of the floating gate above the channel region is replaced with an auxiliary gate. The auxiliary gate serves to control the storage (writing) of a charge in the floating gate for thereby reducing a write current.
However, the technology taught in the above document is not practicable without resorting to the auxiliary gate, resulting in a sophisticated memory cell structure.
It is another object of the present invention to provide a transistor capable of solving the problem described above by increasing writing speed with a simple structure.